Designers strive to decrease the size and power consumption of electronic equipment, while increasing the speed and functionality of the equipment. As this electronic equipment becomes smaller and faster improved control over the power distribution system on an integrated circuit or chip has become a topic of intense effort. Many electronic products or devices have functional systems on a single integrated circuit (IC) or chip. This configuration is often referred to as a “system on a chip” (SoC). A SoC may have circuits such as a core processor, static random access memory (SRAM), cache memory, registers, branching logic, multiplexers, control features and decision logic that accept inputs and creates outputs. Each of these systems can be connected to different power lines or power rails and power to these subsystems can be controlled by a power controller.
This is important because reducing power to idle subsystems or unused portions of an integrated circuit, for example banks of SRAM, can significantly reduce power consumption within an IC and within the device generally. This active-inactive dichotomy also occurs in register banks, register files, multiplexers, and branching logic to name a few. Other circuits commonly found on microchips include pipeline circuits where flip flops are chained in series where bits of data advance from flip-flop to flip-flop where only the part of the chain that is active needs to be powered. Accordingly, in such configurations not all portions of the circuits need to operate concurrently during specific time intervals. To conserve power, and allow for longer battery life, portions of the SoC can be placed in a sleep mode or even shut down when not in use. Also, for some devices, the entire system can be placed in a sleep mode.
In addition, some circuits perform better with and/or require a slow ramp-up voltage from the sleep mode while others such as a phase locked loop can require a fast ramp or need to achieve a stable operating mode before other circuits that utilize their output are activated. For example, a circuit such as a phase locked loop (PLL) typically provides a clock signal to all synchronized circuits in the integrated circuit and thus, a PLL should be running in a stable mode before any synchronized logic attempts to emerge from a sleep mode. Likewise, some circuits can require a slow transition to a sleep mode to make sure that an orderly shut down occurs while other circuits can require a quick shut down in response to many phenomena such as an over-current detection. It can be appreciated that comprehensive and accurate power control can greatly increase the functionality, efficiency and reliability of an IC and of a device and can significantly increase battery life for mobile devices.
Most traditional motherboards have three categories of integrated circuits including system on a chip (SoC)s that consume power and process data, voltage regulators or VRs devices that deliver power, and power management devices to control the VRs for sequencing, faults, etc. Motherboards may have one or more devices in any category. This “separateness” of the VRs and the power management created deficiencies in operation due to time delay, additional interconnect, etc. A significant limitation of traditional power control solutions is that any single power management device does not perform platform-wide control, sequencing, faults, etc. The scope of its control is typically limited to a subset of the rails in the motherboard. Some techniques, such as a master power management device, required a fourth type of device to coordinate these narrow-scope devices. This is significant because the trend in VRs is to make them “faster” (higher-frequency switching VRs that require faster control in case of faults) and the trend in many electronic devices is to rapidly transition between “active” and “sleep” states (which requires complex flexible control of power sequencing).